A typical integrated DC-DC buck converter has a high-side power transistor and a low-side power transistor connected in series between supply terminals, and an external inductor connected between the interconnection node of the power transistors, usually referred to as the switch node, and an output terminal to which a load is connected. At low load, the converter enters a power saving mode which reduces the quiescent current consumption and ensures a high conversion efficiency by skipping switch pulses. This power saving mode is referred to as PFM (Pulse Frequency Modulation) mode, or simply “pulse skipping mode”. An error comparator compares the output voltage at the output terminal with a reference voltage. When the output voltage drops below the reference voltage, the high-side power transistor is switched on during an ON time of a predetermined minimum duration, the switching frequency depending on the load current. This minimum ON time is determined to optimize converter efficiency for the smallest conceived value of the external inductor in view of the smallest and cheapest overall converter solution, still keeping low the output voltage ripple. Since the minimum ON time is optimized for a particular value of the external inductor, the converter efficiency is less for bigger values of an external inductor. Catalog products such as integrated DC-DC converters must of course be open to a range of external inductor values, but at the price of a lower converter efficiency with inductor values bigger than the small inductor value for which the minimum ON time is optimized.